1. Field
The following description relates to a semiconductor device configured to operate effectively at a medium voltage region and a manufacturing method thereof.
2. Description of Related Art
Various technologies are being developed to improve a Hot Carrier Immunity (HCI) characteristic of a device to lower a magnitude of an electric field generated around a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET).
Referring to FIG. 1, a gate oxide film 12 and a gate conductive film 11 are formed on a substrate 10, and an LDD region 13 is formed by implanting dopants having a low doping concentration at a tilt angle. A sidewall spacer 14 is formed; then, a source 16 and a drain 15 are formed by implanting dopants of an N-type having a high doping concentration.
In the MOSFET structure, there is a certain limiting value for a formable LDD region length (Lo). In order to apply a sub-micron device, a gate length may be equal to or less than 55 nm, and a thickness of the gate conductive film should be equal to or less than 100 nm.
Regarding the thin gate conductive film having a thickness of less than 100 nm, the formable LDD length (Lo) has a certain limiting value. If an ion implantation with a higher energy sufficient to pass the gate electrode for formation of laterally extended LDD region is implemented, implanted dopants may penetrate into a semiconductor region under the gate electrode. As a result, an implanted LDD region is formed at the channel region under the gate. If this occurs, the transistor cannot be functional as a MOSFET.
Therefore, the more high-end technology gets, the more limitations exist for applicable energy to implant ions at a tilt angle. Accordingly, a length (Lo) of the LDD region is limited.
Furthermore, the more high-end technology gets, the more the thickness of the LDD spacer for large scale integration is reduced. For this reason, a region of high doping concentration extends to a channel region which is farther and then the channel region becomes small, such that an electric field is increased. Accordingly, Ioff and Isub.max become high when the LDD spacer becomes small.
In addition, if a length (Lo) of an LDD region is not sufficient, an electric field is concentrated at a drain and thus, a bulk current becomes large. Accordingly, the Hot Carrier Immunity (HCI) characteristic is degraded. The more high-end technology gets, the more intensified the above-mentioned problems becomes. The MOSFET used for an AMP of a driver IC requires flatness regarding a drain voltage-drain current characteristic at a low gatevoltage for a matching characteristic between transistors. But, if a bulk current increases due to an insufficient Lo, a drain current is drastically increased. Accordingly, flatness cannot be maintained, and so-called snapback is thus increased. Ultimately, an offset characteristic of an amplifier circuit is degraded, such that production of a driver IC cannot be realized.
Due to such limitations in high-end technology, a MOSFET structure having a high bulk current is not suitable for producing a transistor device necessary for a driver IC to drive an AMOLED applied to a smartphone and so forth.
That is, in order to drive an AMOLED used for a display device such as smartphones, LED TVs, PC monitors, and notebooks; the MOSFET that stably operates is required. Here, the characteristics required by the device are: 1) a probability of large scale integration, 2) a high driving current, 3) a small leakage current, 4) a low bulk current for a small snapback to be suitable for an AMP of a driver IC, and 5) a high reliability of Hot Carrier Immunity (HCI).
However, as explained above, the more high-end technology gets, the greater the limitations for length (Lo) of a formable LDD region in the MOSFET structure there are. Further, due to a small spacer, an electric field is increased.